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K7M163625M K7M161825M
Document Title
512Kx36 & 1Mx18 Flow-Through NtRAM TM
512Kx36 & 1Mx18-Bit Flow Through NtRAMTM
Revision History
Rev. No. 0.0 0.1 0.2 History 1. Initial document. 1. Update ICC & ISB values. 1. Change tOE from 3.5ns to 4.0ns at -8 . 2. Change tOE from 3.5ns to 4.0ns at -9 . 3. Change tOE from 3.5ns to 4.0ns at -10 . 1. Change ISB value from 60mA to 80mA at -8. 2. Change ISB value from 50mA to 70mA at -9 . 3. Change ISB value from 40mA to 60mA at -10 . 1. Changed tCYC from 12ns to 10ns at -9 . 2. Changed DC condition at Icc and parameters Icc ; from 300mA to 320mA at -8, from 260mA to 300mA at -9, from 240mA to 280mA at -10 3. Change pin allocation at 119BGA . - A4 ; from NC to A . - B2 ; from A to CS2 - B4 ; from CKE to ADV - B6 ; from A to CS2 - G4 ; from ADV to A - H4 ; from NC to WE - M4 ; from WE toCKE 1. Final Spec Release. Add access time 7.5ns bin. 1. Remove -10 bin ( tCD=10ns) Nov. 19. 1999 Preliminary Draft Date March. 25. 1999 May. 27. 1999 June. 22. 1999 Remark Preliminary Preliminary Preliminary
Sep. 04. 1999 0.3
Preliminary
0.4
1.0 2.0 3.0
Dec. 08. 1999 Nov. 23. 2000 Feb. 23. 2001
Final Final Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to c hange the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
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February 2001 Rev 3.0
K7M163625M K7M161825M
512Kx36 & 1Mx18 Flow-Through NtRAM TM
512Kx36 & 1Mx18-Bit Flow Through NtRAMTM
FEATURES
* 3.3V+0.165V/-0.165V Power Supply. * I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O * Byte Writable Function. * Enable clock and suspend operation. * Single READ/WRITE control pin. * Self-Timed Write Cycle. * Three Chip Enable for simple depth expansion with no data contention . * A interleaved burst or a linear burst mode. * Asynchronous output enable control. * Power Down mode. * TTL-Level Three-State Outputs. * 100-TQFP-1420A /119BGA(7x17 Ball Grid Array Package).
GENERAL DESCRIPTION
The K7M163625M and K7M161825M are 18,874,368-bits Synchronous Static SRAMs. The N tRAM TM , or No Turnaround Random Access Memory utilizes all bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied "High or Low". Asynchronous inputs include the sleep mode enable(ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. For read cycles, Flow-Through SRAM allows output data to simply flow freely from the memory array. The K7M163625M and K7M161825M are implemented with SAMSUNG s high performance CMOS technology and is available in 100pin TQFP and 119BGA packages. Multiple power and ground pins minimize ground bounce.
FAST ACCESS TIMES
Parameter Cycle Time Clock Access Time Output Enable Access Time Symbol -75 -85 -90 Unit tCYC tCD tOE 8.5 10 10 9.0 4.0 ns ns ns
7.5 8.5 4.0 4.0
LOGIC BLOCK DIAGRAM
LBO A [0:18]or A [0:19] ADDRESS REGISTER A2 ~A18 or A2 ~A19 A0~A1 BURST ADDRESS COUNTER A0~A1 512Kx36 , 1Mx18 MEMORY ARRAY
CLK CKE
K
WRITE ADDRESS REGISTER K DATA-IN REGISTER
CONTROL LOGIC
CS1 CS2 CS2 ADV WE BWx (x=a,b,c,d or a,b) OE ZZ
DQa0 ~ DQd7 or DQa0 ~ DQb8 DQPa ~ DQPd
CONTROL REGISTER
CONTROL LOGIC BUFFER
36 or 18
NtRAMT M and No Turnaround Random Access Memory are trademarks of Samsung.
-2-
February 2001 Rev 3.0
K7M163625M K7M161825M
PIN CONFIGURATION (TOP VIEW)
BWd
512Kx36 & 1Mx18 Flow-Through NtRAM TM
BWb
BWa
BWc
CKE
ADV
CLK
CS1
CS2
CS2
VDD
VSS
WE
A18
A17 83
OE
A6
A7
A8 82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
V SS
N.C.
N.C.
L BO
VDD
A5
A4
A3
A2
A1
A0
A10
A11
A12
A13
A14
A15
PIN NAME
SYMBOL A0 - A18 PIN NAME Address Inputs TQFP PIN NO. SYMBOL VDD VSS N.C. DQa0~a7 DQb0~b7 DQc0~c7 DQd0~d7 DQPa~Pd VDDQ VSSQ PIN NAME TQFP PIN NO. 32,33,34,35,36,37,44 45,46,47,48,49,50,81 82,83,84,99,100 ADV Address Advance/Load 85 WE Read/Write Control Input 88 CLK Clock 89 CKE Clock Enable 87 CS1 Chip Select 98 CS2 Chip Select 97 CS2 Chip Select 92 BWx(x=a,b,c,d) Byte Write Inputs 93,94,95,96 OE Output Enable 86 ZZ Power Sleep Mode 64 LBO Burst Mode Control 31 Power Supply(+3.3V) 15,16,41,65,91 Ground 14,17,40,66,67,90 No Connect Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs 38,39,42,43 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30
Output Power Supply 4,11,20,27,54,61,70,77 (2.5V or 3.3V) Output Ground 5,10,21,26,55,60,71,76
Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
-3-
A16
50
DQPc DQc0 DQc1 VDDQ VSSQ DQc2 DQc3 DQc4 DQc5 VSSQ VDDQ DQc6 DQc7 Vss V DD V DD VSS DQd 0 DQd 1 VDDQ VSSQ DQd 2 DQd 3 DQd 4 DQd 5 VSSQ VDDQ DQd 6 DQd 7 DQPd
81
A9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 Pin TQFP
(20mm x 14mm)
K7M163625M(512Kx36)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQPb DQb7 DQb6 VDDQ VSSQ DQb5 DQb4 DQb3 DQb2 VSSQ VDDQ DQb1 DQb0 VSS VSS VDD ZZ DQa7 DQa6 VDDQ VSSQ DQa5 DQa4 DQa3 DQa2 VSSQ VDDQ DQa1 DQa0 DQPa
February 2001 Rev 3.0
K7M163625M K7M161825M
PIN CONFIGURATION (TOP VIEW)
512Kx36 & 1Mx18 Flow-Through NtRAM TM
BWb
BWa
CKE
N.C.
ADV
CS2 N.C.
CLK
CS1
CS2
VDD
VSS
WE
A19
A18 83
OE
A6
A7
A8 82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
V SS
N.C.
N.C.
L BO
VDD
A5
A4
A3
A2
A1
A0
A11
A12
A13
A14
A15
A16
PIN NAME
SYMBOL A 0 - A19 PIN NAME Address Inputs TQFP PIN NO. 32,33,34,35,36,37,44 45,46,47,48,49,50,80 81,82,83,84,99,100 85 88 89 87 98 97 92 93,94 86 64 31 SYMBOL VDD VSS N.C. PIN NAME Power Supply(+3.3V) Ground No Connect TQFP PIN NO. 15,16,41,65,91 14,17,40,66,67,90 1,2,3,6,7,25,28,29,30, 38,39,42,43,51,52,53, 56,57,75,78,79,95,96 58,59,62,63,68,69,72,73,74 8,9,12,13,18,19,22,23,24
ADV WE CLK CKE CS 1 CS 2 CS 2 BW x(x=a,b) OE ZZ LBO
Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Power Sleep Mode Burst Mode Control
DQa0~a8 DQb0~b8
Data Inputs/Outputs Data Inputs/Outputs
VDDQ VSSQ
Output Power Supply (2.5V or 3.3V) Output Ground
A17
50
N.C. N.C. N.C. VDDQ VSSQ N.C. N.C. DQb 8 DQb 7 VSSQ VDDQ DQb 6 DQb 5 VSS V DD V DD VSS DQb 4 DQb 3 VDDQ VSSQ DQb 2 DQb 1 DQb 0 N.C. VSSQ VDDQ N.C. N.C. N.C.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
81
A9 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
100 Pin TQFP
(20mm x 14mm)
K7M161825M(1Mx18)
A10 N.C. N.C. VDDQ VSSQ N.C. DQa0 DQa1 DQa2 VSSQ VDDQ DQa3 DQa4 VSS VSS VDD ZZ DQa5 DQa6 VDDQ VSSQ DQa7 DQa8 N.C. N.C. VSSQ VDDQ N.C. N.C. N.C.
4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76
Notes : 1. A0 and A 1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
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February 2001 Rev 3.0
K7M163625M K7M161825M
512Kx36 & 1Mx18 Flow-Through NtRAM TM
119BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW)
K7M163625M(512Kx36)
1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQc DQc VDDQ DQc DQc VDDQ DQd DQd VDDQ DQd DQd NC NC VDDQ 2 A CS2 A DQPc DQc DQc DQc DQc V DD DQd DQd DQd DQd DQPd A NC NC 3 A A A V SS V SS V SS BWc V SS NC V SS BWd V SS V SS V SS LBO A NC 4 A ADV V DD NC CS1 OE A WE V DD CLK NC CKE A1* A0* V DD A NC 5 A A A VSS VSS VSS BW b VSS NC VSS BW a VSS VSS VSS NC A NC 6 A CS2 A DQPb DQb DQb DQb DQb V DD DQa DQa DQa DQa DQPa A NC NC 7 VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ
Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
PIN NAME
SYMBOL A A0,A1 ADV WE CLK CKE CS1 CS2 CS2 BWx (x=a,b,c,d) OE ZZ LBO Address Inputs Burst Address Inputs Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs PIN NAME VDD VSS N.C. DQa DQb DQc DQd DQPa~Pd VDDQ Output Enable Power Sleep Mode Burst Mode Control SYMBOL Power Supply Ground No Connect Data Data Data Data Data Inputs/Outputs Inputs/Outputs Inputs/Outputs Inputs/Outputs Inputs/Outputs PIN NAME
Output Power Supply
-5-
February 2001 Rev 3.0
K7M163625M K7M161825M
512Kx36 & 1Mx18 Flow-Through NtRAM TM
119BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW)
K7M161825M(1Mx18)
1 A B C D E F G H J K L M N P R T U
Note :
2 A CS2 A NC DQb NC DQb NC V DD DQb NC DQb NC DQPb A A NC
3 A A A V SS V SS V SS BWb V SS NC V SS V SS V SS V SS V SS LBO A NC
4 A ADV V DD NC CS1 OE A WE V DD CLK NC CKE A1* A0* V DD NC NC
5 A A A VSS VSS VSS VSS VSS NC VSS BW a VSS VSS VSS NC A NC
6 A CS2 A DQPa NC DQa NC DQa V DD NC DQa NC DQa NC A A NC
7 VDDQ NC NC NC DQa VDDQ DQa NC VDDQ DQa NC VDDQ NC DQa NC ZZ VDDQ
VDDQ NC NC DQb NC VDDQ NC DQb VDDQ NC DQb VDDQ DQb NC NC NC VDDQ
* A0 and A 1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
PIN NAME
SYMBOL A A0,A1 ADV WE CLK CKE CS1 CS2 CS2 BWx (x=a,b) OE ZZ LBO Address Inputs Burst Address Inputs Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs PIN NAME VDD VSS N.C. SYMBOL Power Supply Ground No Connect PIN NAME
DQa DQb DQPa, Pb VDDQ
Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Output Power Supply
Output Enable Power Sleep Mode Burst Mode Control
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February 2001 Rev 3.0
K7M163625M K7M161825M
FUNCTION DESCRIPTION
512Kx36 & 1Mx18 Flow-Through NtRAM TM
The K7M163625M and K7M161825M are N tRAM TM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write, or vice versa. All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges. All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by th e burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next operation. Clock Enable( CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous inputs are ignored and the internal device registers will hold their previous values. NtRAM T M latches external address and initiates a cycle, when CKE , ADV are driven to low and all three chip enables(CS1, CS 2, CS2) are active . Output Enable( OE) can be used to disable the output at any given time. Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the address register, CKE is driven low, all three chip enables(CS 1, CS2, CS 2) are active, the write enable input signals WE are driven high, and ADV driven low. Data appears at the outputs within the same clock cycle as the address for the data. Also during read operation OE must be driven low for the device to drive out the requested data. Write operation occurs when WE is driven low at the rising edge of the clock. BW [d:a] can be used for byte write operation. The Flow Through NtRAMTM uses a late write cycle to utilize 100% of the bandwidth. At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required one cycle later. Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected. And when this pin is high, Interleaved burst sequence is selected. During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. A t this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up time.
BURST SEQUENCE TABLE
LBO PIN HIGH First Address Case 1 A1 0 0 1 1 A0 0 1 0 1 A1 0 0 1 1 Case 2 A0 1 0 1 0 A1 1 1 0 0 Case 3
(Interleaved Burst, LBO=High)
Case 4 A0 0 1 0 1 A1 1 1 0 0 A0 1 0 1 0
Fourth Address
BQ TABLE
LBO PIN LOW First Address Case 1 A1 0 0 1 1 A0 0 1 0 1 A1 0 1 1 0 Case 2 A0 1 0 1 0 A1 1 1 0 0 Case 3
(Linear Burst, LBO=Low)
Case 4 A0 0 1 0 1 A1 1 0 0 1 A0 1 0 1 0
Fourth Address
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
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February 2001 Rev 3.0
K7M163625M K7M161825M
512Kx36 & 1Mx18 Flow-Through NtRAM TM
STATE DIAGRAM FOR NtRAMTM
WRITE READ
READ
BEGIN READ
RE A DS
ST
BEGIN WRITE
D TE RI DS
BU R
WRITE
D
DESELECT
DS
W
WR
RE A
BU R
ST
I TE
B URST
DS
DS
BURST
BURST READ
W
R
IT E D
R E A
BURST WRITE
BURST
COMMAND DS READ WRITE BURST DESELECT BEGIN READ BEGIN WRITE BEGIN READ BEGIN WRITE CONTINUE DESELECT
ACTION
Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does not change the state of the device. 2. States change on the rising edge of the clock(CLK)
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February 2001 Rev 3.0
K7M163625M K7M161825M
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1 H X X X L X L X L X L X X CS2 X L X X H X H X H X H X X CS2 X X H X L X L X L X L X X ADV L L L H L H L H L H L H X WE X X X X H X H X L X L X X BWx X X X X X X X X L L H H X OE X X X X L L H H X X X X X
512Kx36 & 1Mx18 Flow-Through NtRAM TM
CKE L L L L L L L L L L L L H
CLK
ADDRESS ACCESSED N/A N/A N/A N/A External Address Next Address External Address Next Address External Address Next Address N/A Next Address Current Address
OPERATION Not Selected Not Selected Not Selected Not Selected Continue Begin Burst Read Cycle Continue Burst Read Cycle NOP/Dummy Read Dummy Read Begin Burst Write Cycle Continue Burst Write Cycle NOP/Write Abort Write Abort Ignore Clock
Notes : 1. X means "Dont Care".
2. The rising edge of clock is symbolized by ().
3. A continue deselect cycle can only be enterd if a deselect cycle is executed first. 4. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE. 5. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE( x36)
WE H L L L L L L BWa X L H H H L H BWb X H L H H L H BWc X H H L H L H BWd X H H H L L H OPERATION READ WRITE BYTE a WRITE BYTE b WRITE BYTE c WRITE BYTE d WRITE ALL BYTEs WRITE ABORT/NOP
Notes : 1. X means "Dont Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK( ).
WRITE TRUTH TABLE(x18)
WE H L L L L
Notes : 1. X means "Don t Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK().
BWa X L H L H
BWb X H L L H
OPERATION READ WRITE BYTE a WRITE BYTE b WRITE ALL BYTEs WRITE ABORT/NOP
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February 2001 Rev 3.0
K7M163625M K7M161825M
ASYNCHRONOUS TRUTH TABLE
Operation Sleep Mode Read Write Deselected ZZ H L L L L OE X L H X X
512Kx36 & 1Mx18 Flow-Through NtRAM TM
I/O STATUS High-Z DQ High-Z Din, High-Z High-Z
Notes 1. X means "Don t Care". 2. Sleep Mode means power Sleep Mode of which stand-by current does not depend on cycle time. 3. Deselected means power Sleep Mode of which stand-by current depends on cycle time.
ABSOLUTE MAXIMUM RATINGS*
PARAMETER Voltage on VDD Supply Relative to VSS Voltage on Any Other Pin Relative to VSS Power Dissipation Storage Temperature Operating Temperature Storage Temperature Range Under Bias SYMBOL VDD VIN PD TSTG TOPR TBIAS RATING -0.3 to 4.6 -0.3 to 4.6 1.6 -65 to 150 0 to 70 -10 to 85 UNIT V V W C C C
*Notes : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING CONDITIONS at 3.3V I/O(0 C TA 70C)
PARAMETER Supply Voltage Ground SYMBOL VDD V DDQ V SS MIN 3.135 3.135 0 Typ. 3.3 3.3 0 MAX 3.465 3.465 0 UNIT V V V
OPERATING CONDITIONS at 2.5V I/O(0 C TA 70C)
PARAMETER Supply Voltage Ground SYMBOL VDD V DDQ V SS MIN 3.135 2.375 0 Typ. 3.3 2.5 0 MAX 3.465 2.9 0 UNIT V V V
CAPACITANCE* (TA=25C, f=1MHz)
PARAMETER Input Capacitance Output Capacitance
*Note : Sampled not 100% tested.
SYMBOL CIN COUT
TEST CONDITION V IN=0V V OUT=0V
MIN -
MAX 7 9
UNIT pF pF
- 10 -
February 2001 Rev 3.0
K7M163625M K7M161825M
512Kx36 & 1Mx18 Flow-Through NtRAM TM
DC ELECTRICAL CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0C to +70C)
PARAMETER Input Leakage Current(except ZZ) Output Leakage Current SYMBOL IIL IOL TEST CONDITIONS V DD=Max ; VIN=VSS to VDD Output Disabled, -75 Operating Current ICC Device Selected, IOUT =0mA, ZZ VIL , Cycle Time tCYC Min Device deselected, IOUT =0mA, ISB ZZ VIL, f=Max, All Inputs 0.2V or V DD -0.2V Standby Current ISB1 -85 -90 -75 -85 -90 MIN -2 -2 MAX +2 +2 340 320 300 90 80 70 30 mA mA mA 1,2 UNIT NOTES A A
Device deselected, IOUT =0mA, ZZ0.2V, f=0, All Inputs=fixed (V DD-0.2V or 0.2V) Device deselected, IOUT =0mA, ZZVDD -0.2V, f=Max, All Inputs VIL or V IH IOL=8.0mA IOH=-4.0mA IOL=1.0mA IOH=-1.0mA
ISB2 Output Low Voltage(3.3V I/O) Output High Voltage(3.3V I/O) Output Low Voltage(2.5V I/O) Output High Voltage(2.5V I/O) Input Low Voltage(3.3V I/O) Input High Voltage(3.3V I/O) Input Low Voltage(2.5V I/O) Input High Voltage(2.5V I/O) VOL V OH VOL V OH VIL VIH VIL VIH
2.4 2.0 -0.3* 2.0 -0.3* 1.7
30 0.4 0.4 0.8 VDD +0.5** 0.7 VDD +0.5**
mA V V V V V V V V 3 3
Notes : 1. Reference AC Operating Conditions and Characteristics for input and timing. 2. Data states are all zero. 3. In Case of I/O Pins, the Max. VIH=V D D Q +0.3V.
VIH
VSS
VSS-1.0V 20% tC Y C (MIN)
TEST CONDITIONS
(VDD =3.3V+0.165V/-0.165V,VDDQ=3.3V+0.165/-0.165V or VDD =3.3V+0.165V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA =0to70C) PARAMETER Input Pulse Level(for 3.3V I/O) Input Pulse Level(for 2.5V I/O) Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O) Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O) Input and Output Timing Reference Levels for 3.3V I/O Input and Output Timing Reference Levels for 2.5V I/O Output Load VALUE 0 to 3.0V 0 to 2.5V 1.0V/ns 1.0V/ns 1.5V VDDQ/2 See Fig. 1
- 11 -
February 2001 Rev 3.0
K7M163625M K7M161825M
Output Load(A)
512Kx36 & 1Mx18 Flow-Through NtRAM TM
Output Load(B), (for tLZC, tLZOE, tHZOE & tHZC) RL=50 30pF* VL=1.5V for 3.3V I/O V DDQ/2 for 2.5V I/O Dout 353 / 1538 +3.3V for 3.3V I/O /+2.5V for 2.5V I/O 319 / 1667
Dout Zo=50
5pF*
* Including Scope and Jig Capacitance Fig. 1
AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0 C to +70C)
-75 PARAMETER Cycle Time Clock Access Time Output Enable to Data Valid Clock High to Output Low-Z Output Hold from Clock High Output Enable Low to Output Low-Z Output Enable High to Output High-Z Clock High to Output High-Z Clock High Pulse Width Clock Low Pulse Width Address Setup to Clock High CKE Setup to Clock High Data Setup to Clock High Write Setup to Clock High ( WE, BWX) Address Advance Setup to Clock High Chip Select Setup to Clock High Address Hold from Clock High CKE Hold from Clock High Data Hold from Clock High Write Hold from Clock High (WE , BWX) Address Advance Hold from Clock High Chip Select Hold from Clock High ZZ High to Power Down ZZ Low to Power Up SYMBOL tCYC tCD tOE tLZC tOH tLZOE tHZOE tHZC tCH tCL tAS tCES tDS tWS tADVS tCSS tAH tCEH tDH tWH tADVH tCSH tPDS tPUS MIN 8.5 2.5 2.5 0 2.5 2.5 2.0 2.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 0.5 0.5 2 2 MAX 7.5 4.0 4.0 5.0 MIN 10 2.5 2.5 0 3.0 3.0 2.0 2.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 0.5 0.5 2 2 -85 MAX 8.5 4.0 4.0 5.0 MIN 10 2.5 2.5 0 3.0 3.0 2.0 2.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 0.5 0.5 2 2 -90 MAX 9.0 4.0 4.0 5.0 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cycle cycle
Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled. 3. A write cycle is defined by WE low having been registerd into the device at ADV Low, A Read cycle is defined by WE High with ADV Low, Both cases must meet setup and hold times. 4. To avoid bus contention, At a given vlotage and temperature tL Z C is more than tHZC. The soecs as shown do not imply bus contention because tL Z C is a Min. parameter that is worst case at totally different test conditions (0C,3.465V) than tHZC , which is a Max. parameter(worst case at 70 C,3.135V) It is not possible for two SRAMs on the same board to be at such different voltage and temperatue.
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February 2001 Rev 3.0
K7M163625M K7M161825M
SLEEP MODE
512Kx36 & 1Mx18 Flow-Through NtRAM TM
SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of SLEEP MODE is dictated by the length of time the ZZ is in a High state. After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE. When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. Any operation pending when entering SLEEP MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pending operations are completed. similarly, when exiting SLEEP MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SLEEP MODE.
SLEEP MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION Current during SLEEP MODE ZZ active to input ignored CONDITIONS ZZ VIH SYMBOL ISB2 tPDS tPUS tZZI tRZZI 0 2 2 2 MIN MAX 10 UNITS mA cycle cycle cycle
ZZ inactive to input sampled
ZZ active to SLEEP current ZZ inactive to exit SLEEP current
SLEEP MODE WAVEFORM
K
tPDS ZZ setup cycle tPUS ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2 tRZZI
All inputs (except ZZ)
Deselect or Read Only
Deselect or Read Only
Normal operation cycle
Outputs (Q)
High-Z
DONT CARE
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February 2001 Rev 3.0
TIMING WAVEFORM OF READ CYCLE
tC H tCL
Clock
tCYC tCES tCEH
K7M163625M K7M161825M
CKE
tAS A1 A2 A3
tAH
Address
tWS
tWH
WRITE
- 14 tCSH tADVH tOE tHZOE tOH Q2- 1 Q 2-2 Q2- 3 Q2 -4 tLZOE Q1 -1 tCD
tCSS
CS
tADVS
ADV
OE
tHZC
Data Out
Q3- 1
Q3- 2
Q 3-3
Q3-4
February 2001
512Kx36 & 1Mx18 Flow-Through NtRAM TM
Dont Care Undefined
Rev 3.0
NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
TIMING WAVEFORM OF WRTE CYCLE
tC H tCL
Clock
tCYC
K7M163625M K7M161825M
tCES tCEH
CKE
Address
A2 A3
A1
WRITE
- 15 D1-1 tH ZOE D2-1 D2-2 D2 -3 D2-4
CS
ADV
OE
tDS D3 -1 D3- 2 tD H D3 -3 D3-4
Data In
Data O ut
Q0- 4
Dont Care Undefined
February 2001
512Kx36 & 1Mx18 Flow-Through NtRAM TM
Rev 3.0
NOT ES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and C S2 = H, or CS1 = L, and CS2 = L
TIMING WAVEFORM OF SINGLE READ/WRITE
tCH tCL
Clock
tCYC
K7M163625M K7M161825M
tCES tC EH
CKE
Address
A2 A3 A4 A5 A6 A7
A1
WRITE
- 16 Q1 Q3 Q4 tDS D2 tDH D5
CS
ADV
OE
tOE tLZOE Q6 Q7
Data O ut
Data In
February 2001
512Kx36 & 1Mx18 Flow-Through NtRAM TM
Dont Care Undefined
Rev 3.0
NOTES : WRITE = L means WE = L, and BWx = L CS = L means C S1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
TIMING WAVEFORM OF CKE OPERATION
tCH tCL
Clock
tCYC
K7M163625M K7M161825M
tCES tCEH
CKE
Address
A2 A3 A4
A1
A5
WRITE
- 17 tHZC Q1 Q3 tDS D2 tDH
CS
ADV
OE
tCD tLZC
Data Out
Q4
Data In
February 2001
Dont Care Undefined
512Kx36 & 1Mx18 Flow-Through NtRAM TM
Rev 3.0
NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
TIMING WAVEFORM OF CS OPERATION
tCH tCL
Clock
tC EH tCYC
K7M163625M K7M161825M
tCES
CKE
Address
A2 A3 A4 A5
A1
WRITE
- 18 tHZC tCD tLZC Q4 tDS tDH D3 Q1 Q2
CS
ADV
OE
tOE tLZOE
Data O ut
Data In
D5
February 2001
Dont Care Undefined
512Kx36 & 1Mx18 Flow-Through NtRAM TM
Rev 3.0
NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and C S2 = L
K7M163625M K7M161825M
PACKAGE DIMENSIONS
100-TQFP-1420A
22.00 0 . 3 0 20.00 0 . 2 0
512Kx36 & 1Mx18 Flow-Through NtRAM TM
Units ; millimeters/Inches
0~8 0.127 +- 0 ..1 0 0 05
16.00 0 . 3 0 14.00 0.20 0.10 MAX
(0.83) 0.50 0.10 #1 0.65 0.30 0 . 1 0 0.10 MAX (0.58)
1.40 0.10 0.50 0.10 0.05 MIN
1.60 MAX
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February 2001 Rev 3.0
K7M163625M K7M161825M
119BGA PACKAGE DIMENSIONS
14.00 0.10
512Kx36 & 1Mx18 Flow-Through NtRAM TM
1.27
1.27
22.00 0.10 Indicator of Ball(1A) Location
20.500.10
C1.00
C0.70 0.7500.15
0.600.10 12.500.10
1.50REF 0.60 0.10 Notes 1. All Dimensions are in Millimeters. 2. Solder Ball to PCB Offset : 0.10 MAX. 3. PCB to Cavity Offset : 0.10 MAX.
- 20 -
February 2001 Rev 3.0

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